The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Jan. 29, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyunsoo Chung, Hwaseong-si, KR;

Jongyeon Kim, Suwon-si, KR;

In-Young Lee, Yongin-si, KR;

Tae-Je Cho, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01); H01L 21/02 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/03 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/02016 (2013.01); H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/76898 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 24/92 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/50 (2013.01); H01L 24/16 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.


Find Patent Forward Citations

Loading…