The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Jul. 31, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Jing-Cheng Lin, Hsin-Chu, TW;

Jeffrey Chang, Hsin-Chu, TW;

Chun-Hsing Su, New Taipei, TW;

Tsei-Chung Fu, Toufen Township, TW;

Yi-Chao Mao, Zhongli, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3114 (2013.01); H01L 21/565 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/94 (2013.01); H01L 2924/18162 (2013.01);
Abstract

An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers. The device package further includes one or more fan-out redistribution layers (RDLs) electrically connected to the semiconductor die, wherein the one or more fan-out RDLs extend past edges of the semiconductor die onto a top surface of the planarizing polymer layer.


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