The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Sep. 20, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ling Wu, Singapore, SG;

Jianbo Yang, Singapore, SG;

Kian Hong Lim, Singapore, SG;

Sung Mun Jung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 27/115 (2017.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 27/11521 (2017.01); H01L 29/06 (2006.01); H01L 27/11548 (2017.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 27/11526 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/28273 (2013.01); H01L 21/76802 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 29/0619 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/788 (2013.01);
Abstract

Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.


Find Patent Forward Citations

Loading…