The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Jul. 22, 2015
Applicant:

Floadia Corporation, Kodaira-shi, Tokyo, JP;

Inventors:

Yasuhiro Taniguchi, Kodaira, JP;

Yutaka Shinagawa, Kodaira, JP;

Hideo Kasai, Kodaira, JP;

Ryotaro Sakurai, Kodaira, JP;

Tatsuro Toya, Kodaira, JP;

Yasuhiko Kawashima, Kodaira, JP;

Kosuke Okuyama, Kodaira, JP;

Assignee:

FLOADIA CORPORATION, Kodaira-Shi, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 11/419 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 14/009 (2013.01); G11C 11/419 (2013.01); G11C 13/0069 (2013.01);
Abstract

A first switch transistor and a second switch transistor are turned on concurrently. Thereby a first ReRAM is electrically connected to a first storage node, and a second ReRAM is electrically connected to a second storage node. Complementary SRAM data stored in an SRAM is programmed into a non-volatile memory section of a first memory cell and a second memory cell. One of the first switch transistor and the second switch transistor is turned on to electrically connect only the first ReRAM to the first storage node or to electrically connect only the second ReRAM to the second storage node. Hence, the first memory cell or the second memory cell functions as an independent-type cell in accordance with usage. Data is programmed separately into the first memory cell Mor the second memory cell M. Thus memory capacity is increased.


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