The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Aug. 03, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Tang-Chun Weng, Chiayi, TW;

Chia-Ching Lin, Kaohsiung, TW;

Yen-Pu Chen, Tainan, TW;

En-Chiuan Liou, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 21/66 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3088 (2013.01); H01L 21/3081 (2013.01); H01L 21/76224 (2013.01); H01L 22/12 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.


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