The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Apr. 07, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Shahrukh A. Khan, Danbury, CT (US);

Unoh Kwon, Fishkill, NY (US);

Shahab Siddiqui, White Plains, NY (US);

Sean M. Polvino, Watertown, MA (US);

Joseph F. Shepard, Jr., Poughkeepsie, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/311 (2006.01); H01L 29/51 (2006.01); H01L 21/033 (2006.01); H01L 21/84 (2006.01); H01L 21/027 (2006.01); H01L 21/8234 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42364 (2013.01); H01L 21/0273 (2013.01); H01L 21/0332 (2013.01); H01L 21/31133 (2013.01); H01L 21/31144 (2013.01); H01L 21/823462 (2013.01); H01L 21/845 (2013.01); H01L 27/1207 (2013.01); H01L 29/511 (2013.01); H01L 29/518 (2013.01);
Abstract

One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.


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