The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Mar. 23, 2012
Applicants:

Byung Tai DO, Singapore, SG;

Arnel Senosa Trasporto, Singapore, SG;

Linda Pei EE Chua, Singapore, SG;

Inventors:

Byung Tai Do, Singapore, SG;

Arnel Senosa Trasporto, Singapore, SG;

Linda Pei Ee Chua, Singapore, SG;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49861 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 21/4828 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/81 (2013.01); H01L 24/96 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48177 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/96 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1029 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/16152 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer.


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