The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Jul. 25, 2014
Applicant:

Xintec Inc., Jhongli, Taoyuan County, TW;

Inventors:

Ching-Yu Ni, Hsinchu, TW;

Chia-Ming Cheng, New Taipei, TW;

Nan-Chun Lin, New Taipei, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/498 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3192 (2013.01); H01L 24/06 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15788 (2013.01); H01L 2924/16195 (2013.01); H01L 2924/16235 (2013.01);
Abstract

A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.


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