The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Oct. 14, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wan-Yu Lee, Taipei, TW;

Chun-Hao Tseng, Taichung, TW;

Jui Hsieh Lai, Taoyuan, TW;

Tien-Yu Huang, Shuishang Township, TW;

Ying-Hao Kuo, Hsin-Chu, TW;

Kuo-Chung Yee, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/31 (2006.01); H01L 33/54 (2010.01); H01L 33/52 (2010.01); H01L 31/0203 (2014.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 25/16 (2006.01); G02B 6/12 (2006.01); G02B 6/42 (2006.01); H01L 31/02 (2006.01); H01L 33/62 (2010.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31 (2013.01); G02B 6/12002 (2013.01); G02B 6/12004 (2013.01); G02B 6/4214 (2013.01); H01L 21/311 (2013.01); H01L 21/56 (2013.01); H01L 23/31 (2013.01); H01L 23/315 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 25/167 (2013.01); H01L 25/50 (2013.01); H01L 31/02002 (2013.01); H01L 31/0203 (2013.01); H01L 33/52 (2013.01); H01L 33/54 (2013.01); H01L 33/62 (2013.01); G02B 2006/12104 (2013.01); G02B 2006/12147 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13091 (2013.01);
Abstract

An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.


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