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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9793281 B1

PDFFull Text
Date of Patent:
Oct. 17, 2017

Filed:

Jun. 13, 2016

Non-volatile split gate memory cells with integrated high k metal gate logic device and metal-free erase gate, and method of making same

Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Chien-Sheng Su, Saratoga, CA (US);

Jeng-Wei Yang, Zhubei, TW;

Feng Zhou, Fremont, CA (US);

Assignee:

Silicon Storage Technology, Inc., San Jose, CA (US);

Attorney:

DLA Piper LLP US

Primary Examiner:

Abul Kalam

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11531 (2017.01); H01L 27/11524 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 29/42328 (2013.01); H01L 29/66484 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

Find Patent Forward Citations

Su, Chien-Sheng. (2017). Non-volatile split gate memory cells with integrated high k metal gate logic device and metal-free erase gate, and method of making same (U.S. Patent No. 9793281). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9793281

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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