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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9793233 B1

PDFFull Text
Expired
Date of Patent:
Oct. 17, 2017

Filed:

Aug. 01, 2016

Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajasekaran Swaminathan, Tempe, AZ (US);

Leonel R. Arana, Phoenix, AZ (US);

Yoshihiro Tomita, Tsukuba, JP;

Yosuke Kanaoka, Tsukuba, JP;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:

Konrad Raynes Davda & Victor LLP

Alan S. Raynes

Primary Examiner:

Zandra Smith

Assistant Examiner:

Lawrence Tynes, Jr

Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 24/16 (2013.01); H01L 21/4853 (2013.01); H01L 23/3157 (2013.01); H01L 23/49816 (2013.01); H01L 23/49894 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H05K 3/3484 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/16012 (2013.01); H01L 2224/16147 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H05K 3/3452 (2013.01); H05K 2203/043 (2013.01); H05K 2203/083 (2013.01); H05K 2203/1476 (2013.01);
Abstract

Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Find Patent Forward Citations

Swaminathan, Rajasekaran. (2017). Forming sacrificial composite materials for package-on-package architectures and structures formed thereby (U.S. Patent No. 9793233). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9793233

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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