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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9788416 B1

PDFFull Text
Date of Patent:
Oct. 10, 2017

Filed:

Dec. 22, 2014

Multilayer substrate for semiconductor packaging

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wei-Lun Kane Jen, Chandler, AZ (US);

Padam Jain, Davis, CA (US);

Dilan Seneviratne, Chandler, AZ (US);

Chi-Mon Chen, Chandler, AZ (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt, P.C.

Primary Examiner:

Eduardo A Rodela

Int. Cl.
CPC ...
H01L 23/13 (2006.01); H05K 1/02 (2006.01); H01L 21/02 (2006.01); H01L 23/12 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H05K 1/18 (2006.01); H01L 25/065 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0271 (2013.01); H01L 21/02002 (2013.01); H01L 21/02008 (2013.01); H01L 21/02035 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/12 (2013.01); H01L 23/13 (2013.01); H01L 23/3185 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/15311 (2013.01); H05K 1/0298 (2013.01); H05K 1/0393 (2013.01); H05K 1/181 (2013.01); H05K 2201/0191 (2013.01); H05K 2201/05 (2013.01);
Abstract

Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.

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