The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Dec. 08, 2015
Applicant:

Disco Corporation, Tokyo, JP;

Inventors:

Yohei Yamashita, Tokyo, JP;

Kenji Furuta, Tokyo, JP;

Yihui Lee, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/78 (2006.01); H01L 21/304 (2006.01); H01L 21/683 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/304 (2013.01); H01L 21/6836 (2013.01); H01L 23/544 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2223/54433 (2013.01); H01L 2223/54486 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A wafer processing method for dividing a wafer into individual device chips along division lines is disclosed. The wafer processing method includes a back grinding step of grinding the back side of the wafer in the condition where a protective tape is attached to the front side of the wafer, thereby reducing the thickness of the wafer to a predetermined thickness, and a reinforcing insulation seal mounting step of mounting a reinforcing insulation seal capable of transmitting infrared light on the back side of the wafer. The wafer processing method further includes a modified layer forming step of applying a laser beam along each division line to thereby form a modified layer inside the wafer along each division line and a wafer dividing step of applying an external force to the wafer to thereby divide the wafer into the individual device chips along each division line.


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