The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2017

Filed:

Nov. 30, 2016
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Cheng-Chou Hung, Hukou Township, Hsinchu County, TW;

Ming-Tzong Yang, Baoshan Township, Hsinchu County, TW;

Tung-Hsing Lee, New Taipei, TW;

Wei-Che Huang, Zhudong Township, Hsinchu County, TW;

Yu-Hua Huang, Hsinchu, TW;

Tzu-Hung Lin, Zhubei, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 29/06 (2006.01); H01L 21/761 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/761 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/11 (2013.01); H01L 29/0619 (2013.01); H01L 29/0623 (2013.01); H01L 2224/13 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.


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