The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2017
Filed:
May. 12, 2016
International Business Machines Corporation, Armonk, NY (US);
Tokyo Electron Limited, Tokyo, JP;
Stmicroelectronics, Inc., Coppell, TX (US);
Yannick Feurprier, Watervliet, NY (US);
Joe Lee, Albany, NY (US);
Lars W. Liebmann, Poughquag, NY (US);
Yann Mignot, Slingerlands, NY (US);
Terry A. Spooner, Clifton Park, NY (US);
Douglas M. Trickett, Altamont, NY (US);
Mehmet Yilmaz, Ankara, TR;
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
TOKYO ELECTRON LIMITED, Tokyo, JP;
STMICROELECTRONICS, INC., Coppell, TX (US);
Abstract
A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.