The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Oct. 06, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Mayank Parasrampuria, Jaipur, IN;

Anurag Jindal, Patiala, IN;

Sagar Kataria, Noida, IN;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318385 (2013.01); G01R 31/31705 (2013.01); G01R 31/318547 (2013.01);
Abstract

An integrated circuit (IC) includes a logic built-in self-test (LBIST) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. A debug controller receives the scan out signals and shifts a set of the scan out signals to a joint test action group (JTAG) controller. The debug controller also maintains a dynamic count indicative of the number of debug shift operations performed, and compares the dynamic count with a final count. If the dynamic count is less than the final count, the debug controller performs a second debug shift operation, which facilitates determination of a fault location in the IC.


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