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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9761607 B1

PDFFull Text
Date of Patent:
Sep. 12, 2017

Filed:

Dec. 22, 2014

Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate

Applicant:

Commissariat a L'energie Atomique ET Aux Ene Alt, Paris, FR;

Inventors:

Shay Reboh, Sassenage, FR;

Perrine Batude, Dijon, FR;

Sylvain Maitrejean, Grenoble, FR;

Frederic Mazen, Saint Egreve, FR;

Assignee:

Commissariat à l'énergie atomique et aux énergies alternatives, Paris, FR;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Julio J Maldonado

Assistant Examiner:

Moin Rahman

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/04 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 27/092 (2006.01); H01L 21/265 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/0217 (2013.01); H01L 21/02115 (2013.01); H01L 21/02186 (2013.01); H01L 21/02422 (2013.01); H01L 21/02532 (2013.01); H01L 21/02609 (2013.01); H01L 21/02667 (2013.01); H01L 21/30604 (2013.01); H01L 21/76251 (2013.01); H01L 21/84 (2013.01); H01L 29/04 (2013.01); H01L 29/7843 (2013.01); H01L 29/7847 (2013.01); H01L 21/26506 (2013.01); H01L 21/823807 (2013.01); H01L 27/092 (2013.01);
Abstract

A method for producing a microelectronic device is provided, including forming on an insulating layer of a semi-conductor on insulator type substrate, a first semi-conductor block covered with a first strain zone configured to induce a compressive strain in the first block and a second semi-conductor block covered with a second strain zone configured to induce a tensile strain in the second block, the first block and the second block each being formed of a lower region based on amorphous semi-conductor material, covered with an upper region of crystalline semi-conductor material in contact with one of the strain zones; and recrystallizing the lower region of the first and second blocks while using the upper region of crystalline material as starting zone for a recrystallization front.

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