The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Jul. 08, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Qing Ma, Saratoga, CA (US);

Chuan Hu, Chandler, AZ (US);

Patrick Morrow, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 23/498 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01); H01L 21/48 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/3675 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H05K 3/42 (2013.01); H05K 3/4605 (2013.01); B32B 2457/08 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/0102 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01011 (2013.01); H01L 2924/01012 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01016 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01024 (2013.01); H01L 2924/01025 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01051 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15184 (2013.01); H01L 2924/15788 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/096 (2013.01); Y10T 156/10 (2015.01);
Abstract

Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.


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