The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Mar. 21, 2016
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Hsueh-Shih Fan, Hsinchu, TW;
Ching-Fang Huang, Taipei, TW;
Chia-Hsin Hu, Changhua, TW;
Min-Chang Liang, Zhu-Dong Town, TW;
Sun-Jay Chang, Hsinchu, TW;
Shien-Yang Wu, Jhudong Town, TW;
Wen-Hsing Hsieh, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsin-Chu, TW;
Abstract
Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.