The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Aug. 17, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co. Ltd., Hsin-Chu, TW;

Inventors:

Yue-Der Chih, Hsin-Chu, TW;

Hung-Chang Yu, Hsin-Chu, TW;

Kai-Chun Lin, Hsinchu, TW;

Chin-Yi Huang, Hsinchu, TW;

Laun C. Tran, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); H03M 13/00 (2006.01); G06F 11/10 (2006.01); H03M 13/11 (2006.01); G06F 11/14 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1056 (2013.01); G06F 11/10 (2013.01); G06F 11/1004 (2013.01); G06F 11/1048 (2013.01); G06F 11/1052 (2013.01); G06F 11/141 (2013.01); G06F 11/1402 (2013.01); G11C 11/1675 (2013.01); G11C 11/1677 (2013.01); H03M 13/11 (2013.01); H03M 13/611 (2013.01); G11C 2013/0076 (2013.01);
Abstract

Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location.


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