The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Jun. 17, 2015
Applicant:

Kinsus Interconnect Technology Corp., Taoyuan, TW;

Inventors:

Jaen-Don Lan, New Taipei, TW;

Pin-Chung Lin, New Taipei, TW;

Chen-Rui Tseng, Taoyuan, TW;

Cheng-En Ho, New Taipei, TW;

Yu-An Chen, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/46 (2006.01); B23K 26/402 (2014.01); H05K 3/42 (2006.01); B23K 26/382 (2014.01); B23K 103/00 (2006.01);
U.S. Cl.
CPC ...
B23K 26/402 (2013.01); B23K 26/389 (2015.10); H05K 3/426 (2013.01); H05K 3/4644 (2013.01); B23K 2203/30 (2015.10); B23K 2203/50 (2015.10); H05K 2201/0341 (2013.01);
Abstract

Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.


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