The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2017

Filed:

Feb. 10, 2016
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Shinko Electric Industries Co., Ltd, Nagano-Shi, JP;

Inventors:

Edmund Blackshear, Wappingers Falls, NY (US);

Keiichi Hirabayashi, Nagano, JP;

Yoichi Miyazawa, White Plains, NY (US);

Brian W. Quinlan, Poughkeepsie, NY (US);

Junji Sato, Nagano, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/32 (2006.01); H05K 3/40 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/185 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 3/0047 (2013.01); H05K 3/32 (2013.01); H05K 3/4038 (2013.01); H05K 3/4644 (2013.01); H05K 2201/0959 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10522 (2013.01); H05K 2203/16 (2013.01);
Abstract

A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.


Find Patent Forward Citations

Loading…