The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2017

Filed:

May. 11, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chao-Hsuing Chen, Tainan, TW;

Ling-Sung Wang, Tainan, TW;

Chi-Yen Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/26506 (2013.01); H01L 21/30604 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/7848 (2013.01);
Abstract

Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.


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