The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2017

Filed:

Jan. 29, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Thomas N. Adam, Slingerlands, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Ali Khakifirooz, Mountain View, CA (US);

Alexander Reznicek, Troy, NY (US);

Raghavasimhan Sreenivasan, Schenectady, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/28 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78648 (2013.01); H01L 21/28008 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/42364 (2013.01);
Abstract

A semiconductor device is disclosed. The semiconductor device can include a first dielectric layer disposed on a substrate; a set of bias lines disposed on the first dielectric layer; a second dielectric layer disposed on the first dielectric layer and between the set of bias lines, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; a patterned semiconductor layer disposed on portions of the second dielectric layer; and a set of devices disposed on the patterned semiconductor layer above the set of bias lines.


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