The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Jan. 21, 2016
Silicon Storage Technology, Inc., San Jose, CA (US);
Jeng-Wei Yang, Zhubei, TW;
Chun-Ming Chen, New Taipei, TW;
Man-Tang Wu, Xinpu Township, Hsinchu County, TW;
Feng Zhou, Fremont, CA (US);
Xian Liu, Sunnyvale, CA (US);
Chien-Sheng Su, Saratoga, CA (US);
Nhan Do, Saratoga, CA (US);
SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US);
Abstract
A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.