The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Oct. 04, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Patrick Morrow, Portland, OR (US);
Don Nelson, Beaverton, OR (US);
M. Clair Webb, Aloha, OR (US);
Kimin Jun, Hillsboro, OR (US);
Il-Seok Son, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/20 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/74 (2006.01); H01L 23/50 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/2007 (2013.01); H01L 21/743 (2013.01); H01L 23/50 (2013.01); H01L 23/522 (2013.01); H01L 23/5286 (2013.01); H01L 24/18 (2013.01); H01L 27/1207 (2013.01);
Abstract
Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.