The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2017

Filed:

Jun. 28, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin J. Lee, Beaverton, OR (US);

Hiten Kothari, Beaverton, OR (US);

Wayne M. Lytle, Banks, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/525 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76885 (2013.01); H01L 23/525 (2013.01); H01L 23/53238 (2013.01); H01L 23/481 (2013.01); H01L 2224/1182 (2013.01); H01L 2224/13565 (2013.01);
Abstract

An embodiment includes a semiconductor apparatus comprising: a redistribution layer (RDL) including a patterned RDL line having two RDL sidewalls, the RDL comprising a material selected from the group comprising Cu and Au; protective sidewalls directly contacting the two RDL sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the RDL line has a RDL line width orthogonal to and extending between the two RDL sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the RDL line width. Other embodiments are described herein.


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