The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2017
Filed:
Apr. 29, 2016
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Zhiwei Gong, Chandler, AZ (US);
Wei Gao, Tianjin, CN;
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4853 (2013.01); H01L 23/49816 (2013.01); H01L 24/09 (2013.01); H01L 25/162 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); H05K 3/34 (2013.01); H05K 3/3436 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48091 (2013.01); H05K 2201/10674 (2013.01); H05K 2201/10734 (2013.01);
Abstract
A method of forming a semiconductor device assembly includes forming an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The method further includes attaching the first major surface of the interposer to a packaged semiconductor device, wherein the opening of the interposer exposes the packaged semiconductor device.