The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2017

Filed:

Sep. 27, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Henning Braunisch, Phoenix, AZ (US);

Feras Eid, Chandler, AZ (US);

Adel A. Elsherbini, Chandler, AZ (US);

Johanna M. Swan, Scottsdale, AZ (US);

Don W. Nelson, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/52 (2006.01); H01L 23/473 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 21/52 (2013.01); H01L 23/367 (2013.01); H01L 23/473 (2013.01); H01L 23/49811 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.


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