The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2017

Filed:

Sep. 09, 2016
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Emmanuel Augendre, Montbonnot, FR;

Aomar Halimaoui, La Terrasse, FR;

Sylvain Maitrejean, Grenoble, FR;

Shay Reboh, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02694 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/266 (2013.01); H01L 21/26586 (2013.01); H01L 21/823412 (2013.01); H01L 21/84 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66568 (2013.01);
Abstract

A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG.A).


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