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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9698093 B1

PDFFull Text
Date of Patent:
Jul. 04, 2017

Filed:

Aug. 24, 2015

Universal bga substrate

Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Chee Seng Foong, Austin, TX (US);

Ly Hoon Khoo, Petaling Jaya, MY;

Wen Shi Koh, Petaling Jaya, MY;

Wai Yew Lo, Petaling Jaya, MY;

Zi Song Poh, Petaling Jaya, MY;

Kai Yun Yow, Petaling Jaya, MY;

Assignee:

NXP USA,INC., Austin, TX (US);

Attorney:

Charles E. Bergere

Primary Examiner:

Teresa M Arroyo

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/48 (2006.01); H01L 23/544 (2006.01); G03F 9/00 (2006.01); H01L 23/538 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4853 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 24/49 (2013.01); H01L 24/85 (2013.01); H01L 24/97 (2013.01); G03F 9/7073 (2013.01); G03F 9/7084 (2013.01); H01L 21/486 (2013.01); H01L 21/76816 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/5384 (2013.01); H01L 23/544 (2013.01); H01L 2223/544 (2013.01); H01L 2223/5446 (2013.01); H01L 2224/13009 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/48235 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01);
Abstract

A universal substrate for assembling ball grid array (BGA) type integrated circuit packages has a non-conducting matrix, an array of conducting vias extending between top and bottom surfaces of the matrix, and one or more instances of each of two or more different types of fiducial pairs on the top surface of the matrix. Each instance of each different fiducial pair indicates a location of a different via sub-array of the substrate for a different BGA package of a particular package size. The same substrate can be used to assemble BGA packages of different size, thereby avoiding having to design a different substrate for each different BGA package size.

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