The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Mar. 27, 2014
Applicants:

Seong Won Park, Icheon-si, KR;

Hun Teak Lee, Seongnam-si, KR;

Woonjae Beak, Cheongju-si, KR;

Minjung Kim, Kwang-ju, KR;

Changhwan Kim, Cheonan-si, KR;

Byunghyun Kwak, Icheon-si, KR;

Gwangtae Kim, Seoul, KR;

Heesoo Lee, Anyang-si, KR;

Inventors:

Seong Won Park, Icheon-si, KR;

Hun Teak Lee, Seongnam-si, KR;

WoonJae Beak, Cheongju-si, KR;

MinJung Kim, Kwang-ju, KR;

ChangHwan Kim, Cheonan-si, KR;

ByungHyun Kwak, Icheon-si, KR;

GwangTae Kim, Seoul, KR;

HeeSoo Lee, Anyang-si, KR;

Assignee:

STATS ChipPAC Pte. Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/36 (2006.01); H05K 3/40 (2006.01); H05K 1/09 (2006.01); H05K 1/18 (2006.01); H05K 1/14 (2006.01); H05K 3/32 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/112 (2013.01); H05K 1/09 (2013.01); H05K 1/113 (2013.01); H05K 3/36 (2013.01); H05K 3/4038 (2013.01); H05K 1/14 (2013.01); H05K 1/18 (2013.01); H05K 3/32 (2013.01); H05K 3/46 (2013.01); H05K 2201/04 (2013.01);
Abstract

A system and method of manufacture of an integrated circuit packaging system includes: a copper film; a first metal layer directly on the copper film; an insulation layer directly on and over the first metal layer, the insulation layer having a via hole through the insulation layer; a conductive via within the via hole and directly on the first metal layer; a second metal layer directly on the conductive via and the insulation layer; a copper post directly on the copper film; a solder pad over the copper post; and an interposer coupled to the copper post and the solder pad.


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