The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Apr. 30, 2013
Applicants:

Jane A. Yater, Austin, TX (US);

Cheong Min Hong, Austin, TX (US);

Sung-taeg Kang, Austin, TX (US);

Ronald J. Syzdek, Austin, TX (US);

Inventors:

Jane A. Yater, Austin, TX (US);

Cheong Min Hong, Austin, TX (US);

Sung-Taeg Kang, Austin, TX (US);

Ronald J. Syzdek, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/42332 (2013.01);
Abstract

A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.


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