The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Nov. 16, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jie Deng, San Jose, CA (US);

Pranita Kerber, Mount Kisco, NY (US);

Qiqing C. Ouyang, Yorktown Heights, NY (US);

Alexander Reznicek, Troy, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.


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