The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Aug. 11, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Zhenyu Lu, Milpitas, CA (US);

Johann Alsmeier, San Jose, CA (US);

Daxin Mao, Cupertino, CA (US);

Wenguang Shi, Milpitas, CA (US);

Sateesh Koka, Milpitas, CA (US);

Raghuveer S. Makala, Campbell, CA (US);

George Matamis, Danville, CA (US);

Yao-Sheng Lee, Tampa, FL (US);

Chun Ge, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

A monolithic three-dimensional memory device includes a first memory block containing a plurality of memory sub-blocks located on a substrate. Each memory sub-block includes a set of memory stack structures and a portion of alternating layers laterally surrounding the set of memory stack structures. The alternating layers include insulating layers and electrically conductive layers. A first portion of a neighboring pair of memory sub-blocks is laterally spaced from each other along a first horizontal direction by a backside contact via structure. A subset of the alternating layers contiguously extends between a second portion of the neighboring pair of memory sub-blocks through a gap in a bridge region between two portions of the backside contact via structure that are laterally spaced apart along a second horizontal direction to provide a connecting portion between the neighboring pair of memory sub-blocks.


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