The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Sep. 13, 2016
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Jinho Kim, Saratoga, CA (US);

Chien-Sheng Su, Saratoga, CA (US);

Feng Zhou, Fremont, CA (US);

Xian Liu, Sunnyvale, CA (US);

Nhan Do, Saratoga, CA (US);

Prateep Tuntasood, San Jose, CA (US);

Parviz Ghazavi, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 27/11531 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01);
Abstract

A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.


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