The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Apr. 22, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Hsin Ko, Fongshan, TW;

Hung-Wei Chen, Hsin-Chu, TW;

Chung-Hu Ke, Taipei, TW;

Wen-Chin Lee, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/10 (2006.01); H01L 29/47 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 29/1054 (2013.01); H01L 29/47 (2013.01); H01L 29/665 (2013.01); H01L 29/6653 (2013.01); H01L 29/6659 (2013.01); H01L 29/66568 (2013.01); H01L 29/66643 (2013.01); H01L 29/7843 (2013.01); H01L 29/165 (2013.01);
Abstract

A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.


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