The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
Jul. 29, 2010
Lee-chung LU, Taipei, TW;
Yi-kan Cheng, Taipei, TW;
Chung-hsing Wang, Hsin-Chu County, TW;
Chen-fu “alex” Huang, Kaohsiung, TW;
Hsiao-shu Chao, Hsin-Chu County, TW;
Chin-yu Chiang, Taipei County, TW;
Ho Che Yu, Zhebei, TW;
Chih Sheng Tsai, Taichung County, TW;
Shu Yi Ying, Taichung, TW;
Lee-Chung Lu, Taipei, TW;
Yi-Kan Cheng, Taipei, TW;
Chung-Hsing Wang, Hsin-Chu County, TW;
Chen-Fu “Alex” Huang, Kaohsiung, TW;
Hsiao-Shu Chao, Hsin-Chu County, TW;
Chin-Yu Chiang, Taipei County, TW;
Ho Che Yu, Zhebei, TW;
Chih Sheng Tsai, Taichung County, TW;
Shu Yi Ying, Taichung, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.