The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Nov. 10, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shubhada H. Sahasrabudhe, Gilbert, AZ (US);

Sandeep B Sane, Chandler, AZ (US);

Siddarth Kumar, Chandler, AZ (US);

Shalabh Tandon, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 2224/1607 (2013.01); H01L 2224/16055 (2013.01); H01L 2224/16057 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81365 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/81951 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01);
Abstract

Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.


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