The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2017
Filed:
Oct. 20, 2015
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Yung-Hsu Wu, Taipei, TW;
Hai-Ching Chen, Hsinchu, TW;
Jung-Hsun Tsai, Taoyuan, TW;
Shau-Lin Shue, Hsinchu, TW;
Tien-I Bao, Dayuan Township, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TX (US);
Abstract
A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile