The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Jul. 28, 2015
Applicant:

Siliconware Precision Industries Co., Ltd., Taichung, TW;

Inventors:

Hong-Da Chang, Taichung, TW;

Shih-Kuang Chiu, Taichung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 21/683 (2006.01); H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6835 (2013.01); H01L 21/561 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68368 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.


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