The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Mar. 31, 2014
Applicants:

Stmicroelectronics, Inc., Coppell, TX (US);

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John H. Zhang, Altamont, NY (US);

Lawrence A. Clevenger, LaGrangeville, NY (US);

Carl Radens, LaGrangeville, NY (US);

Yiheng Xu, Hopewell Junction, NY (US);

Richard Stephen Wise, Ridgefield, CT (US);

Terry Spooner, Clifton Park, NY (US);

Nicole A. Saulnier, Albany, NY (US);

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/36 (2012.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.


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