The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Sep. 25, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mathew J. Manusharow, Phoenix, AZ (US);

Daniel N. Sobieski, Phoenix, AZ (US);

Mihir K. Roy, Chandler, AZ (US);

William J. Lambert, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/32 (2006.01); H01L 21/768 (2006.01); H01L 21/3205 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/02263 (2013.01); H01L 21/28556 (2013.01); H01L 21/32 (2013.01); H01L 21/3205 (2013.01); H01L 21/768 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01);
Abstract

A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).


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