The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Mar. 25, 2015
International Business Machines Corporation, Armonk, NY (US);
Stmicroelectronics, Inc., Coppell, TX (US);
Globalfoundries Inc., Cayman Islands, KY;
Kangguo Cheng, Schenectady, NY (US);
Bruce B. Doris, Brewster, NY (US);
Ali Khakifirooz, Mountain View, CA (US);
Qing Liu, Guilderland, NY (US);
Nicolas Loubet, Guilderland, NY (US);
Scott Luning, Albany, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
STMICROELECTRONICS, INC., Coppell, TX (US);
GLOBALFOUNDRIES INC., Cayman Islands, KY;
Abstract
A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.