The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2017

Filed:

Jul. 09, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Liang Liao, Taichung, TW;

Chia-Yao Liang, Tainan, TW;

Jui-Long Chen, Taichung, TW;

Sheng-Yuan Lin, Hsinchu, TW;

Yi-Lii Huang, Zhubei, TW;

Kuo-Hsi Lee, Taichung, TW;

Po-An Chen, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/283 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 21/32055 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 29/0649 (2013.01); H01L 29/42364 (2013.01);
Abstract

A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.


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