The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2017
Filed:
Mar. 12, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Anna M. Prakash, Chandler, AZ (US);
James C. Matayabas, Gilber, AZ (US);
Arjun Krishnan, Chandler, AZ (US);
Nisha Ananthakrishnan, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/29 (2006.01); C08K 5/00 (2006.01); H01L 21/78 (2006.01); B23K 26/18 (2006.01); B23K 26/364 (2014.01);
U.S. Cl.
CPC ...
C08K 5/005 (2013.01); B23K 26/18 (2013.01); B23K 26/364 (2015.10); H01L 21/563 (2013.01); H01L 21/78 (2013.01); H01L 2924/0002 (2013.01);
Abstract
Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.