The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 2017

Filed:

Sep. 29, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shih-Hsien Chen, Zhubei, TW;

Liang-Tai Kuo, Zhudong Township, TW;

Hau-Yan Lu, Hsinchu, TW;

Chun-Yao Ko, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/10 (2006.01); H01L 29/49 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 27/11558 (2017.01); H01L 29/66 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1095 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/11558 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01); H01L 29/66181 (2013.01); H01L 29/94 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.


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