The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2017
Filed:
Dec. 14, 2015
Hongning Yang, Chandler, AZ (US);
Daniel J. Blomberg, Chandler, AZ (US);
Jiang-kai Zuo, Chandler, AZ (US);
Hongning Yang, Chandler, AZ (US);
Daniel J. Blomberg, Chandler, AZ (US);
Jiang-Kai Zuo, Chandler, AZ (US);
NXP USA, INC., Austin, TX (US);
Abstract
A multi-region () lateral-diffused-metal-oxide-semiconductor (LDMOS) device () has a semiconductor-on-insulator (SOI) support structure () on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region () and a substantially asymmetric, laterally edge-proximate, second LDMOS region (). A deep trench isolation (DTI) wall () substantially laterally terminates the laterally edge-proximate second LDMOS region (). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region () associated with the DTI wall () are avoided by providing a doped SC buried layer region () in the SOI support structure () proximate the DTI wall (), underlying a portion of the laterally edge-proximate second LDMOS region () and of opposite conductivity type than a drain region () of the laterally edge-proximate second LDMOS region ().