The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Jun. 06, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Shing-Kuei Lai, Taichung, TW;

Wei-Yueh Tseng, Hsinchu, TW;

Hsiao-Yi Wang, Zhunan Township, Miaoli County, TW;

De-Fang Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 21/268 (2006.01); G03F 9/00 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); G03F 7/20 (2013.01); G03F 9/7088 (2013.01); H01L 21/2686 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54433 (2013.01); H01L 2223/54453 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor wafer is provided. The semiconductor wafer includes a base layer having an active region and an edge region. A number of semiconductor devices is formed on the active region. The semiconductor wafer also includes a wafer identification. The wafer identification is formed on the edge region and used for identifying the semiconductor wafer. The semiconductor wafer further includes an alignment mark. The alignment mark is formed on the edge region and is used for performing an alignment process of the semiconductor wafer.


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