The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 2017

Filed:

Feb. 05, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

He Ren, San Jose, CA (US);

Mehul B. Naik, San Jose, CA (US);

Yong Cao, San Jose, CA (US);

Mei-yee Shek, Palo Alto, CA (US);

Yana Cheng, San Jose, CA (US);

Sree Rangasai V. Kesapragada, Union City, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/02178 (2013.01); H01L 21/02266 (2013.01); H01L 21/28556 (2013.01); H01L 21/28562 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.


Find Patent Forward Citations

Loading…